Semiconductor device and method for manufacturing the same

ABSTRACT

A highly reliable semiconductor device exhibiting stable electrical characteristics is provided. Further, a highly reliable semiconductor device is provided. Oxide semiconductor films are stacked so that the conduction band has a well-shaped structure. A second oxide semiconductor film having a crystalline structure is provided over the first oxide semiconductor film and a third oxide semiconductor film is provided over the second oxide semiconductor film. The bottom of a conduction band in the second oxide semiconductor film is deeper from a vacuum level than the bottom of a conduction band in the first oxide semiconductor film and the bottom of a conduction band in the third oxide semiconductor film.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including anoxide semiconductor and a method for manufacturing the semiconductordevice.

In this specification, a semiconductor device generally means a devicewhich can function by utilizing semiconductor characteristics, and anelectrooptic device, a semiconductor circuit, and an electronicappliance are all semiconductor devices.

2. Description of the Related Art

In recent years, semiconductor devices have been developed to be usedmainly for a CPU, or a memory. A CPU is an aggregation of semiconductorelements each provided with an electrode which is a connection terminal,which includes a semiconductor integrated circuit (including at least atransistor and a memory) separated from a semiconductor wafer.

A semiconductor circuit (IC chip) of a CPU or a memory is mounted on acircuit board, for example, a printed wiring board, to be used as one ofcomponents of a variety of electronic appliances.

A technique for manufacturing a transistor or the like using an oxidesemiconductor film for a channel formation region and applying it to adisplay device has been attracting attention. Examples of such atransistor include a transistor in which zinc oxide (ZnO) is used as anoxide semiconductor film and a transistor in which InGaO₃(ZnO)_(m) isused as an oxide semiconductor film.

A technique for manufacturing transistor including an oxidesemiconductor film over a light-transmitting substrate and applying itto a switching element or the like of an image display device isdisclosed in Patent Documents 1 and 2.

Patent Document 3 discloses a semiconductor device in which a transistorincluding an oxide semiconductor is provided over a single crystalsubstrate.

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.    2007-123861-   [Patent Document 2] Japanese Published Patent Application No.    2007-096055-   [Patent Document 3] Japanese Published Patent Application No.    2011-109079

SUMMARY OF THE INVENTION

The electrical characteristics of a transistor including an oxidesemiconductor film are varied by influence of an insulating film incontact with the oxide semiconductor film, that is, by an interfacestate between the oxide semiconductor film and the insulating film.

Further, a transistor including an oxide semiconductor film in whichmany oxygen vacancies have been generated in the manufacturing processhas low long-term reliability. Therefore, it is required to manufacturea transistor including an oxide semiconductor film which has as fewoxygen vacancies as possible. Further, it is required to reduce damageto the oxide semiconductor film which is caused by exposure of the oxidesemiconductor film to plasma during or after deposition of the oxidesemiconductor film.

In view of the above problems, an object of one embodiment of thepresent invention is to provide a highly reliable semiconductor devicewhich exhibits stable electrical characteristics. Another object is tomanufacture a highly reliable semiconductor device.

A buried-channel transistor in which two or more oxide semiconductorfilms are stacked so that an oxide semiconductor having a small numberof oxygen vacancies serves as a carrier path is manufactured.

Specifically, a transistor having a multi-layer structure ismanufactured in which a second oxide semiconductor film having acrystalline structure is stacked over a first oxide semiconductor film,and at least a third oxide semiconductor film is provided over thesecond oxide semiconductor film.

The second oxide semiconductor film is separated from a siliconinsulating film which is located below the second oxide semiconductorfilm by the first oxide semiconductor film, and the third oxidesemiconductor film reduces damage to the second oxide semiconductor filmwhich is caused at the time of exposure to plasma in deposition of asilicon insulating film located over the second oxide semiconductor filmor in etching after formation of a conductive film.

One embodiment of the present invention disclosed in this specificationis a semiconductor device including a first oxide semiconductor film, asecond oxide semiconductor film having a crystalline structure over thefirst oxide semiconductor film, and a third oxide semiconductor filmover the second oxide semiconductor film. In the band structure of thesemiconductor device, the bottom of a conduction band in the secondoxide semiconductor film is deeper from the vacuum level than the bottomof a conduction band in the first oxide semiconductor film and thebottom of a conduction band in the third oxide semiconductor film.

FIG. 1A illustrates an example of a cross section of a transistor. Atransistor 410 includes a gate electrode 401, a first gate insulatingfilm 402 a which is a silicon nitride film, a second gate insulatingfilm 402 b which is a silicon oxide film, a first oxide semiconductorfilm 403 a, a second oxide semiconductor film 403 b, a third oxidesemiconductor film 403 c, and electrode layers 405 a and 405 bfunctioning as source and drain electrodes, over a substrate 400 havingan insulating surface. Further, protective insulating films 407 a and407 b which are silicon oxide films and a protective insulating film 408which is silicon nitride film are provided over the third oxidesemiconductor film 403 c.

A material of the second oxide semiconductor film having a crystallinestructure is selected as appropriate so that the conduction band has awell-shaped structure (also referred to as a well structure). FIG. 1Billustrates an example of the well-shaped structure of the conductionband. Note that the schematic view illustrated in FIG. 1B corresponds toan energy band diagram of a cross section taken along line Y1-Y2 in FIG.1A and illustrates only a portion where the stack of oxide semiconductorfilms is positioned between the silicon nitride films.

If silicon or carbon, which is an element belonging to Group 14, iscontained in the oxide semiconductor film as an impurity, it serves as adonor and the oxide semiconductor film becomes an n-type oxidesemiconductor film. Therefore, the concentration of Si contained in eachof the first and third oxide semiconductor films (the concentrationobtained by secondary ion mass spectrometry (SIMS)) is lower than orequal to 3×10¹⁸/cm³, preferably lower than or equal to 3×10¹⁷/cm³.Further, the concentration of carbon contained in each of the first andthird oxide semiconductor films is lower than or equal to 3×10¹⁸/cm³,preferably lower than or equal to 3×10¹⁷/cm³. In particular, in orderthat a large amount of impurities such as elements belonging to Group 14are not mixed into the second oxide semiconductor film, it is preferablethat the second oxide semiconductor film serving as a carrier path beprovided between or surrounded by the first and third oxidesemiconductor films. In other words, the first and third oxidesemiconductor films can also be referred to as barrier layers whichprevent mixing of elements belonging to Group 14 such as silicon to thesecond oxide semiconductor film. Since the barrier layers are providedabove and below the second oxide semiconductor film, needless to say,the second oxide semiconductor film hardly contains impurities such aselements belonging to Group 14. For example, the Si concentration of thesecond oxide semiconductor film is lower than or equal to 3×10¹⁸/cm³,preferably lower than or equal to 3×10¹⁷/cm³, and the carbonconcentration thereof is lower than or equal to 3×10¹⁸/cm³, preferablylower than or equal to 3×10¹⁷/cm³.

Such a stacked-layer structure enables the second oxide semiconductorfilm to serve as a carrier path, so that carriers travel through aregion having a low content of oxygen vacancies. Since carriers flowthrough the region which is separated from the silicon insulating filmswhich are located above and below the stack of the oxide semiconductorfilms, influence of the oxygen vacancies can be reduced.

If hydrogen or moisture is contained as an impurity in the stack ofoxide semiconductor films, it serves as a donor and the oxidesemiconductor films become n-type oxide semiconductor films; therefore,in order to achieve a well-shaped structure, it is valuable to provide aprotective film (a nitride insulating film, typically a silicon nitridefilm, or the like) for preventing the entry of hydrogen or moisture fromthe outside, above and below the stack of oxide semiconductor films.

Another embodiment of the present invention disclosed in thisspecification is a semiconductor device including a first nitrideinsulating film, a first oxide semiconductor film over the first nitrideinsulating film, a second oxide semiconductor film having a crystallinestructure over the first oxide semiconductor film, a third oxidesemiconductor film over the second oxide semiconductor film, and asecond nitride insulating film over the third oxide semiconductor film.In the semiconductor device, the bottom of a conduction band in thesecond oxide semiconductor film is deeper from the vacuum level than thebottom of a conduction band in the first oxide semiconductor film andthe bottom of a conduction band in the third oxide semiconductor film.The semiconductor device can have higher reliability by including thefirst nitride insulating film and the second nitride insulating film.

Each of the oxide semiconductor films included in the multi-layerstructure contains at least indium (In) at a concentration higher thanor equal to 1×10¹⁹/cm³ and is deposited using a sputtering target withwhich a film can be formed by an AC sputtering method or a DC sputteringmethod. When the sputtering target contains indium, the conductivity isincreased; therefore, deposition by an AC sputtering method or a DCsputtering method is facilitated. A material which can be represented asInM1_(X)Zn_(Y)O_(Z) (X≧1, Y>1, Z>0, and M1 is a metal element such as Gaor Hf) is used as each of materials of the first and third oxidesemiconductor films. Note that in the case where Ga is contained in thematerials of the first and third oxide semiconductors, when theproportion of Ga is high, specifically, when a material which can berepresented by InM1_(X)Zn_(Y)O_(Z) where X is larger than 10 is used,powder might be generated in deposition, and it is made difficult toperform deposition by an AC sputtering or a DC sputtering; therefore,such a material is not suitable as a sputtering target.

A material which can be represented as InM2_(X)Zn_(Y)O_(Z) (X≧1, Y≧X,Z>0, and M2 is a metal element such as Ga or Sn) is used as the materialof the second oxide semiconductor film. Further, indium tin oxide thathas a composition which does not contain M2, i.e., the composition inwhich X is 0, or a material which contains indium oxide as a maincomponent can be used for the second oxide semiconductor film.

The materials of the first, second, and third oxide semiconductor filmsare selected as appropriate so that a well-shaped structure in which thebottom of the conduction band in the second oxide semiconductor film isdeeper from the vacuum level than the bottoms of the conduction band inthe first and third oxide semiconductor films. Specifically, the secondoxide semiconductor film is formed using a material which has a higherindium content than the first and third oxide semiconductor films. Thecontents of indium, gallium, or the like in the first, second, and thirdoxide semiconductor films can be compared with each other bytime-of-flight secondary ion mass spectrometry (also referred to asTOF-SIMS) or X-ray photoelectron spectrometry (also referred to as XPS).Note that the ionization potential of an oxide semiconductor can bemeasured by ultraviolet photoelectron spectroscopy (UPS) or the like.Typically, VersaProbe (manufactured by ULVAC-PHI Inc) is used as ameasurement apparatus for UPS. Note that electron affinity refers to anenergy difference between the vacuum level (E_(∞)) and the bottom of theconduction band (E_(c)). An energy band gap (E_(g)) can be measured witha full automatic spectroscopic ellipsometer UT-300. The energy of theconduction band is calculated by deducting the energy band gap from thevalue of the ionization potential; thus a band structure of a singlelayer or a stack of layers can be formed. In this way, it can beconfirmed that a buried channel is formed using the stacked-layerstructure disclosed in this specification. FIGS. 2A and 2B illustrate anexample thereof.

FIG. 2A is data which shows energies from the vacuum level to theconduction band which are calculated on the basis of measurement data ofa sample by a full automatic spectroscopic ellipsometer UT-300. Thesample was formed in the following manner: a 10-nm-thick film was formedin an atmosphere containing oxygen at 100% using a sputtering target ofan In—Ga—Zn oxide having an atomic ratio of In:Ga:Zn=1:1:1; a10-nm-thick film was stacked thereover in an atmosphere containing argonat 100% using a sputtering target of an In—Ga—Zn oxide having an atomicratio of In:Ga:Zn=3:1:2; and a 10-nm-thick film was stacked thereover inan atmosphere containing oxygen at 100% using a sputtering target of anIn—Ga—Zn oxide having an atomic ratio of In:Ga:Zn=1:1:1. FIG. 2B shows aband structure formed on the basis of the data of FIG. 2A. FIG. 2B showsthat a well-shaped structure is formed in which the bottom of theconduction band in the second oxide semiconductor film is deeper fromthe vacuum level than the bottoms of the conduction band in the firstand third oxide semiconductor films.

Since the second oxide semiconductor film having a crystalline structureis stacked over the first oxide semiconductor film, they can be referredto as a hetero structure having different crystalline structures.

When the oxide semiconductor film serving as a semiconductor film of thetransistor has the above stacked-layer structure, the absorptioncoefficient due to localized states of a region where a channel isformed or at least the second oxide semiconductor film can be lower thanor equal to 3×10⁻³/cm when measured by a constant photocurrent method(CPM) (lower than or equal to 3×10¹³/cm³ when converted into density ofstates).

Although one well-shaped structure is formed using the first, second,and the third oxide semiconductor films as an example of thestacked-layer structure, the structure is not particularly limitedthereto; a plurality of well-shaped structures may be formed with thesecond oxide semiconductor film which has a multi-layer structure, andone example thereof is shown in FIG. 3.

As the first, second, and third oxide semiconductor films, any of ac-axis aligned crystalline oxide semiconductor (CAAC-OS) film, apolycrystalline oxide semiconductor film, a microcrystalline oxidesemiconductor film, an amorphous oxide semiconductor film, or the likeis used. Note that the second oxide semiconductor film is preferably aCAAC-OS film. In this specification and the like, a CAAC-OS film refersto an oxide semiconductor film which includes a crystal whose c-axis isaligned in a direction substantially perpendicular to the surface of theoxide semiconductor film. A CAAC-OS film is subjected to structuralanalysis with an X-ray diffraction (XRD) apparatus. For example, whenthe CAAC-OS film including an InGaZnO₄ crystal is analyzed by anout-of-plane method, a peak appears frequently when the diffractionangle (2θ) is around 31°. This peak is derived from the (009) plane ofthe InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS filmhave c-axis alignment, and that the c-axes are aligned in a directionsubstantially perpendicular to the formation surface or the top surfaceof the CAAC-OS film.

The CAAC-OS layer is not completely single crystal nor completelyamorphous. The CAAC-OS film is one of oxide semiconductor filmsincluding a plurality of crystal parts, and most of each crystal partfits inside a cube whose one side is less than 100 nm. Thus, there is acase where a crystal part included in the CAAC-OS film fits a cube whoseone side is less than 10 nm, less than 5 nm, or less than 3 nm. In atransmission electron microscope (TEM) image of the CAAC-OS film, aboundary between crystal parts, that is, a grain boundary is not clearlyobserved. Thus, in the CAAC-OS film, a reduction in electron mobilitydue to the grain boundary is less likely to occur.

In each of the crystals included in the CAAC-OS film, a c-axis isaligned in a direction parallel to a normal vector of a surface wherethe CAAC-OS film is formed or a normal vector of a surface of theCAAC-OS film. Note that the directions of the a-axis and the b-axis ofone crystal may be different from those of another crystal. In thisspecification and the like, a simple term “perpendicular” includes arange from 85° to 95°. In addition, a simple term “parallel” includes arange from −5° to 5°.

In the CAAC-OS layer, distribution of crystal parts is not necessarilyuniform. For example, in the formation process of the CAAC-OS layer, inthe case where crystal growth occurs from a surface side of the oxidesemiconductor film, the proportion of crystal parts in the vicinity ofthe surface of the oxide semiconductor film is higher than that in thevicinity of the surface where the oxide semiconductor film is formed,i.e., the crystallinity is increased in some cases. Further, when oxygenis added to the CAAC-OS layer, crystallinity in a region to which theelement or the oxygen is added is lowered in some cases.

Since the c-axes of the crystals included in the CAAC-OS film arealigned in the direction parallel to a normal vector of a surface wherethe CAAC-OS film is formed or a normal vector of a surface of theCAAC-OS film, the directions of the c-axes may be different from eachother depending on the shape of the CAAC-OS film (the cross-sectionalshape of the surface where the CAAC-OS film is formed or thecross-sectional shape of the surface of the CAAC-OS film). Note thatwhen the CAAC-OS film is formed, the direction of c-axis of the crystalpart is the direction parallel to a normal vector of the surface wherethe CAAC-OS film is formed or a normal vector of the surface of theCAAC-OS film. The crystal part is formed by deposition or by performingtreatment for crystallization such as heat treatment after deposition.

The CAAC-OS film is formed using a sputtering target. Here, methods formanufacturing sputtering targets each including an oxide semiconductorhaving a crystal region in which the direction of the c-axis is parallelto a normal vector of the top surface of the oxide semiconductor will bedescribed (see FIG. 14).

First, raw materials for the sputtering target are weighed (step S101).

Here, an InO_(X) raw material (a raw material of In), a GaO_(Y) rawmaterial (a raw material of Ga), and a ZnO_(Z) raw material (a rawmaterial of Zn) are prepared as raw materials for the sputtering target.Note that X, Y, and Z are each a given positive number; for example, X,Y, and Z are 1.5, 1.5, and 1, respectively. It is needless to say thatthe above raw materials are an example, and raw materials can beselected as appropriate in order to obtain a desired compound. Forexample, a MO_(Y) raw material may be used instead of the GaO_(y) rawmaterial. Note that Sn, Hf, or Al can be used as M. Alternatively, thefollowing lanthanoid may be used as M: La, Ce, Pr, Nd, Sm, Eu, Gd, Tb,Dy, Ho, Er, Tm, Yb, or Lu. Although the case where three kinds of rawmaterials are used is shown as an example in this embodiment, oneembodiment of the present invention is not limited thereto. For example,this embodiment may be applied to the case where four or more kinds ofraw materials are used or the case where one or two kinds of rawmaterials are used.

Next, the InO_(X) raw material, the GaO_(Y) raw material, and theZnO_(Z) raw material are mixed in a predetermined ratio.

For example, the predetermined ratio of the InO_(x) raw material, theGaO_(Y) raw material, and the ZnO_(Z) raw material is 2:2:1, 8:4:3,3:1:1, 1:1:1, 1:3:2, 4:2:3, 1:1:2, 3:1:4, or 3:1:2 in a molar ratio.With the use of a mixed material having such a ratio, a sputteringtarget including an oxide semiconductor having a crystal region in whichthe direction of the c-axis is parallel to a normal vector of the topsurface of the oxide semiconductor can be easily obtained.

More specifically, in the case of forming a sputtering target ofIn—Ga—Zn-based oxide having a composition of In:Ga:Zn=1:1:1 [atomicratio], the raw materials are weighed so that In₂O₃:Ga₂O₃:ZnO=1:1:2[molar ratio].

Note that also in the case where the MO_(Y) raw material is used insteadof the GaO_(Y) raw material, the ratio of the InO_(X) raw material, theMO_(Y) raw material, and the ZnO_(Z) raw material is 2:2:1, 8:4:3,3:1:1, 1:1:1, 1:3:2, 4:2:3, 1:1:2, 3:1:4, or 3:1:2 in a molar ratio.

A method for forming the sputtering target using a wet method isdescribed. The raw materials for the sputtering target are weighed, andthen, the raw materials are ground and mixed with a ball mill or thelike to obtain compound powder. After the mixing of the plurality of rawmaterials, first baking is performed to generate a crystalline oxide.Then, the crystalline oxide is ground to obtain compound power. Thegrain size of the compound powder is greater than or equal to 0.01 μmand less than or equal to 1 μm, preferably greater than or equal to 0.01μm and less than or equal to 0.5 μm, further preferably greater than orequal to 0.01 μm and less than or equal to 0.3 μm. Ion-exchange water,an organic additive, and the like are further mixed into the compoundpowder to form slurry (step S111).

Then, the slurry is poured into a mold provided with amoisture-permeable filter, so that moisture is removed. The mold may beformed using a metal or an oxide and the upper shape thereof isrectangular or rounded. The mold can be provided with one or more holesat the bottom. With the plural holes, moisture of the slurry can beremoved rapidly. A porous resin, cloth, or the like may be used for thefilter.

Moisture is removed from the slurry in such a manner that water isremoved under reduced pressure through the hole provided at the bottomof the mold into which the slurry is poured. Next, the slurry from whichmoisture has been removed under reduced pressure is naturally dried.Thus, the slurry from which moisture has been removed is molded into theinternal shape of the mold (step S113).

Then, second baking is performed on the molded body in an oxygen (O₂)atmosphere at a temperature of 1400° C. (step S114). Through theabove-described steps, the sputtering target can be obtained using a wetmethod.

Next, a method for forming the sputtering target using a dry method isdescribed. The raw materials for the sputtering target are weighed, andthen, the raw materials are ground and mixed with a ball mill or thelike to obtain compound powder (step S121).

The compound powder obtained is spread over a mold, and pressure isapplied thereto with a pressing machine, whereby the raw material powderis molded to obtain a molded body (step S122).

The obtained molded body is placed in a heating apparatus such as anelectric furnace and baked in an oxygen (O₂) atmosphere at a temperatureof 1400° C. (step S123). Note that in this embodiment, a method in whicha molding step and a baking step are separated as in step S122 and stepS123 is referred to as a cold press method. As a comparison example of acold press method, a hot press method in which a molding step and abaking step are concurrently performed is described below.

First, the above-described steps up to step S121 are performed. Thecompound powder obtained is spread over the mold, and pressure isapplied with a pressing machine to the compound powder provided on theinner side of the mold while the mold is heated in an argon (Ar)atmosphere at a temperature of 1000° C. In this manner, pressure isapplied to the compound powder with the compound powder baked, wherebythe compound powder can be molded to obtain a molded body (step S125).

Here, a method for using a sputtering target containing InGaZnO₄ isdescribed.

Deposition of a CAAC-OS film using the sputtering target containingInGaZnO₄ is described below in detail. First, an ion collides with asputtering target to separate a sputtered particle having crystallinity.A crystal grain which is included in the sputtering target has acleavage plane which is parallel to a surface of the sputtering target.The crystal grain has a portion with a weak interatomic bond. At thetime of collision of the ion with the crystal grain, the weakinteratomic bond is cut. Accordingly, the sputtered particle isseparated along the cleavage plane and the portion with the weakinteratomic bond to have a flat-plate-like shape.

Alternatively, part of the crystal grain is separated along the cleavageplane as a particle and exposed to plasma, so that a bond is cut fromthe portion with the weak interatomic bond; as a result, a plurality ofsputtered particles is generated.

When an oxygen cation is used as the ion, plasma damage at thedeposition can be alleviated. Thus, when the ion collides with thesurface of the sputtering target, a reduction in degree of crystallinityof the sputtering target can be prevented.

It is preferable that the separated sputtered particles be positivelycharged. There is no particular limitation on a timing of when thesputtered particle is positively charged, but it is preferablypositively charged by receiving an electric charge when an ion collides.Alternatively, in the case where plasma is generated, the sputteredparticle is preferably exposed to plasma to be positively charged.Further alternatively, an ion which is an oxygen cation is preferablybonded to a side surface, a top surface, or a bottom surface of thesputtered particle, whereby the sputtered particle is positivelycharged.

Next, a situation where a sputtered particle is deposited on adeposition surface (a surface where a film is to be formed) is describedin detail.

In deposition, the deposition surface has a surface on which severalsputtering particles are deposited. In the case where the sputteredparticles are positively charged, the sputtered particles are depositedin a region of the deposition surface, where no sputtered particle hasbeen deposited yet. This is because the sputtered particles which arepositively charged repel with each other.

Further, c-axes of crystals of the sputtered particles deposited in theabove manner are aligned in a direction perpendicular to the depositionsurface; accordingly, a CAAC-OS film is formed as the oxide film.

To form the CAAC-OS film, it is preferable to increase the substratetemperature in deposition, and the substrate temperature is higher thanor equal to 200° C. and lower than or equal to 550° C. Note that theCAAC-OS film is a film which contains a large amount of oxygen and has areduced number of oxygen vacancies.

In the case where steps for sequentially stacking the three oxidesemiconductor films in FIG. 1A in which a buried channel is formed areperformed successively without exposure to the air, a manufacturingapparatus a top view of which is illustrated in FIG. 11 may be used.

The manufacturing apparatus illustrated in FIG. 11 is single wafermulti-chamber equipment, which includes three sputtering devices 10 a,10 b, and 10 c, a substrate supply chamber 11 provided with threecassette ports 14 for holding a process substrate, load lock chambers 12a and 12 b, a transfer chamber 13, substrate heating chambers 15 and 16,and the like. Note that a transfer robot for transferring a substrate tobe treated is provided in each of the substrate supply chamber 11 andthe transfer chamber 13. The atmospheres of the sputtering devices 10 a,10 b, and 10 c, the transfer chamber 13, and the substrate heatingchambers 15 and 16 are preferably controlled so as to hardly containhydrogen and moisture (i.e., as an inert atmosphere, a reduced pressureatmosphere, or a dry air atmosphere). For example, a preferableatmosphere is a dry nitrogen atmosphere in which the dew point ofmoisture is −40° C. or lower, preferably −50° C. or lower. An example ofa procedure of the manufacturing steps with use of the manufacturingapparatus illustrated in FIG. 11 is as follows. The process substrate istransferred from the substrate supply chamber 11 to the substrateheating chamber 15 through the load lock chamber 12 a and the transferchamber 13; moisture attached to the process substrate is removed byvacuum baking in the substrate heating chamber 15; the process substrateis transferred to the sputtering device 10 c through the transferchamber 13; and a first oxide semiconductor film S1 is deposited in thesputtering device 10 c. Then, the process substrate is transferred tothe sputtering device 10 a through the transfer chamber 13 withoutexposure to air, and a second oxide semiconductor film S2 is depositedin the sputtering device 10 a. Then, the process temperature istransferred to the sputtering device 10 b through the transfer chamber13, and a third oxide semiconductor film S3 is deposited in thesputtering device 10 b. If needed, the process substrate is transferredto the substrate heating chamber 16 through the transfer chamber 13without exposure to air and the heat treatment is performed. Asdescribed above, with use of the manufacturing apparatus illustrated inFIG. 11, a manufacturing process can proceed without exposure to air.Further, with of the sputtering devices in the manufacturing apparatusin FIG. 11, a process performed without exposure to the air can beachieved by change of the sputtering target. As the sputtering devicesin the manufacturing apparatus in FIG. 11, a parallel plate sputteringdevice, an ion beam sputtering device, a facing-target sputteringdevice, or the like may be used. In a facing-target type sputteringdevice, an object surface is separated from plasma and thus damage indeposition is small; therefore, a CAAC-OS film having high crystallinitycan be formed.

A high purity gas having a low concentration of impurities such ashydrogen, water, a hydroxyl group, and hydride is used as a depositiongas for depositing the oxide semiconductor film in each of thesputtering devices 10 a, 10 b, and 10 c.

The heat treatment may be performed in the substrate heating chamber 16under reduced pressure, in a nitrogen atmosphere, in an oxygenatmosphere, in ultra-dry air (air in which the moisture amount is lessthan or equal to 20 ppm (−55° C. by conversion into a dew point),preferably less than or equal to 1 ppm, more preferably less than orequal to 10 ppb, in the measurement with the use of a dew point meter inthe cavity ring down laser spectroscopy (CRDS) system), or in a rare gas(argon, helium, or the like) atmosphere. It is preferable that water,hydrogen, and the like be not contained in the nitrogen atmosphere, inthe oxygen atmosphere, in the ultra-dry air, in the rare gas atmosphere,or the like. It is also preferable that the purity of nitrogen, oxygen,or the rare gas which is introduced into a heat treatment apparatus beset to be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher(that is, the impurity concentration is 1 ppm or lower, preferably 0.1ppm or lower).

The semiconductor device of one embodiment of the present inventionincludes a transistor including an oxide semiconductor film or a circuitincluding the transistor. For example, an electronic device whichincludes, as a component, a semiconductor integrated circuit includingan LSI, a CPU, a power device mounted in a power circuit, a memory, athyristor, a converter, an image sensor, or the like; an electro-opticaldevice typified by a liquid crystal display panel; or a light-emittingdisplay device including a light-emitting element is also included inthe category of the semiconductor device.

According one embodiment of the present invention, a highly reliablesemiconductor device including an oxide semiconductor exhibiting stableelectrical characteristics can be provided. A highly reliablesemiconductor device can be manufactured.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are cross-sectional views illustrating one embodiment ofthe present invention.

FIG. 2A is data which shows energies from the vacuum level to theconduction band and FIG. 2B shows a band structure formed on the basisof the data of FIG. 2A.

FIG. 3 is an example of a band structure illustrating one embodiment ofthe present invention.

FIGS. 4A and 4B are cross-sectional views illustrating manufacturingsteps of one embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating one embodiment of thepresent invention.

FIGS. 6A and 6B are each a circuit diagram illustrating one embodimentof the present invention.

FIGS. 7A to 7C are block diagrams illustrating embodiments of thepresent invention.

FIGS. 8A to 8C are a diagram illustrating a display device of oneembodiment of the present invention and circuit diagrams illustratingpixels.

FIG. 9 is a top view illustrating a display device.

FIG. 10 is a cross-sectional view illustrating a display device.

FIG. 11 is a top view illustrating one example of a manufacturingapparatus of a semiconductor device.

FIGS. 12A to 12C illustrate an electronic appliance.

FIGS. 13A to 13C illustrate electronic appliances.

FIG. 14 is a flowchart showing manufacturing steps of a sputteringtarget of one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. However, the presentinvention is not limited to the description below, and it is easilyunderstood by those skilled in the art that modes and details disclosedherein can be modified in various ways without departing from the spiritand the scope of the present invention. Therefore, the present inventionis not construed as being limited to description of the embodiments.

Embodiment 1

In this embodiment, one embodiment of a semiconductor device isdescribed with reference to FIGS. 4A and 4B. In this embodiment, atransistor 311 including a first semiconductor material is provided in alower portion, and a transistor 411 including a second semiconductormaterial is provided in an upper portion.

Here, the first semiconductor material and the second semiconductormaterial are preferably materials having different band gaps. Forexample, the first semiconductor material may be a semiconductormaterial other than an oxide semiconductor (e.g., silicon) and thesecond semiconductor material may be an oxide semiconductor. Atransistor including a material such as silicon can easily operate athigh speed. On the other hand, a transistor including an oxidesemiconductor enables charge to be held for a long time owing to itscharacteristics.

As a substrate 300 used in the semiconductor device, a single crystalsemiconductor substrate or a polycrystalline semiconductor substratemade of silicon or silicon carbide, a compound semiconductor substratemade of silicon germanium or the like, a silicon on insulator (SOI)substrate, or the like can be used. A channel formation region of thetransistor can be formed in or over the semiconductor substrate. Thesemiconductor device in FIGS. 4A and 4B is an example in which thechannel formation region is formed in the semiconductor substrate toform the transistor in the lower portion.

In the semiconductor device in FIGS. 4A and 4B, a single crystal siliconsubstrate is used as the substrate 300, and the transistor 311 is formedusing the single crystal silicon substrate. Single crystal silicon isused as the first semiconductor material. The transistor 311 is ap-channel transistor. The transistor 311 is manufactured by a knownmanufacturing method. In addition, an n-channel transistor can also bemanufactured by the known method on the substrate on which thetransistor 311 is formed. A complementary metal oxide semiconductor(CMOS) circuit can be formed by combining an n-channel transistor and ap-channel transistor as appropriate, whereby a variety of circuits canbe provided.

The transistor 311 includes a channel formation region, a source region,a drain region, a gate insulating film 303, and a gate electrode 301. Anelement isolation insulating film 302 is provided to surround thetransistor 311, and an electrode layer 304 which is electricallyconnected to the transistor 311 is provided over the element isolationinsulating film 302.

A first interlayer insulating film 312 is formed to cover the electrodelayer 304 and the transistor 311. After an opening reaching theelectrode layer 304 is formed in the first interlayer insulating film312 and a conductive film is deposited, planarization is performed bypolishing treatment (e.g., chemical mechanical polishing (CMP)). A firstwiring layer 306 is formed in the opening of the first interlayerinsulating film 312. Then, a conductive film is formed over the firstwiring layer 306 and the first interlayer insulating film 312. Afterthat, the conductive film is selectively removed using a mask to form asecond wiring layer having a desired shape. In this embodiment, thesecond wiring layer has a three-layer structure in which a firstconductive film 307 a that is a titanium film, a second conductive film307 b that is an aluminum film, and a third conductive film 307 c thatis a titanium film are formed in this order.

Next, a second interlayer insulating film 308 covering the second wiringlayer is formed and a barrier layer 310 is stacked. Then, an openingreaching the second wiring layer is formed in the second interlayerinsulating film 308 and the barrier layer 310. After that, a conductivefilm is formed and planarized by CMP or the like, so that a third wiringlayer 309 is formed in the opening.

The barrier layer 310 is provided between the transistor 311 in thelower portion and a transistor 411 in the upper portion. The barrierlayer 310 is provided in order to prevent impurities such as hydrogencontained in the vicinity of the transistor 311 from diffusing into thetransistor 411 in the upper portion. As the barrier layer 310, amaterial film which releases a small amount of hydrogen or does notrelease hydrogen in later heat treatment is preferably used. Thus, thebarrier layer 310 is preferably formed using a dense inorganicinsulating film (e.g., an aluminum oxide film or a silicon nitride film)having a high blocking property of impurities and the like.Specifically, a silicon nitride film which is deposited by a plasma CVDmethod with supply of a mixed gas of silane (SiH₄) and nitrogen (N₂) isused as the barrier layer 310.

Next, the transistor 411 is formed over the barrier layer 310.

A conductive film is formed over the barrier layer and selectivelyetched to form a fourth wiring layer 434 and a gate electrode 491.

After that, an insulating film 435 covering the gate electrode 491 isformed and planarized by CMP or the like.

Then, the first gate insulating film 402 a and the second gateinsulating film 402 b are formed. The first gate insulating film 402 aand the second gate insulating film 402 b each have a thickness greaterthan or equal to 1 nm and less than or equal to 100 nm and can be formedby a sputtering method, an MBE method, a CVD method, a PLD method, anALD method, or the like as appropriate. A silicon nitride film is usedas the first gate insulating film 402 a. The second gate insulating film402 b is preferably formed using an oxide insulating film includingsilicon oxide, gallium oxide, aluminum oxide, silicon oxynitride,silicon nitride oxide, hafnium oxide, tantalum oxide, or the like.Because the second gate insulating film 402 b is in contact with anoxide semiconductor film to be formed later, the second gate insulatingfilm 402 b preferably contains oxygen in excess of the stoichiometriccomposition in the layer (the bulk).

A 20-nm-thick silicon oxide film may be deposited as the second gateinsulating film 402 b by a plasma CVD method, and after the deposition,the silicon oxide film may be subjected to radical oxidation treatmentby microwave plasma treatment for repairing oxygen vacancies. Forexample, a high-density plasma apparatus is used under a condition wherethe power is 3800 W using a power source of 2.45 GHz, the pressure is106.67 Pa, the substrate temperature is 325° C., the flow rate of argonis 900 sccm, and the flow rate of oxygen is 5 sccm. Here, thehigh-density plasma apparatus refers to an apparatus which can achieve aplasma density higher than or equal to 1×10¹¹/cm³. For example, plasmais generated by applying a microwave power of 3 kW to 6 kW. Beforeformation of the second gate insulating film 402 b, plasma treatment inwhich nitrous oxide (N₂O) and a rare gas are introduced may be performedusing a high-density plasma apparatus.

Next, a stack of oxide semiconductor films is formed over the secondgate insulating film 402 b.

The first oxide semiconductor film 403 a and the second oxidesemiconductor film 403 b are formed, subjected to heat treatment, andthen selectively etched using a mask.

In this embodiment, the first oxide semiconductor film 403 a isdeposited at a substrate temperature of room temperature using a targethaving an atomic ratio of In:Ga:Zn=1:3:2. The first oxide semiconductorfilm 403 a has a thickness greater than or equal to 10 nm and less thanor equal to 40 nm, preferably greater than or equal to 20 nm and lessthan or equal to 30 nm. An increase in the thickness of the first oxidesemiconductor film 403 a can prevent diffusion of Si from the base film(insulating film containing silicon). The second oxide semiconductorfilm 403 b having a crystalline structure is deposited at a substratetemperature of 400° C. using a target having an atomic ratio ofIn:Ga:Zn=1:1:1. The second oxide semiconductor film 403 b is a filmincluding crystals which are c-axis-aligned in a direction substantiallyperpendicular to the surface and preferably a CAAC-OS film. The secondoxide semiconductor film 403 b has a thickness greater than or equal to5 nm and less than or equal to 10 nm.

A deposition temperature of the second oxide semiconductor film 403 b ishigher than or equal to 400° C. and lower than or equal to 550° C.,preferably higher than or equal to 450° C. and lower than or equal to500° C. Note that the deposition temperature is within a range oftemperatures at which the already formed wiring layer can withstand. Theheat treatment is performed in reduced pressure or a nitrogen atmosphereat a temperature higher than or equal to 300° C. and lower than or equalto 600° C., preferably higher than or equal to 300° C. lower than orequal to 500° C., further preferably higher than or equal to 350° C. andlower than or equal to 450° C., to remove excess hydrogen (includingwater and a hydroxyl group) (to perform dehydration or dehydrogenation)in the oxide semiconductor films. Then, a high-purity oxygen gas orultra dry air (the amount of moisture is less than or equal to 20 ppm(−55° C. by conversion into a dew point), preferably less than or equalto 1 ppm, further preferably less than or equal to 10 ppb, when measuredwith a dew point meter of a CRDS system) is introduced to the samefurnace while the heating temperature is kept or slowly lowered afterthe heat treatment. Owing the effect of the oxygen gas, oxygen which isa main component of the oxide semiconductor and which has been reducedat the same time as the step for removing impurities by dehydration ordehydrogenation can be supplied.

Next, the third oxide semiconductor film 403 c is formed to be incontact with and cover the top and side surfaces of the second oxidesemiconductor film 403 b. In addition, heat treatment for removingexcess hydrogen (including water and a hydroxyl group) (performingdehydration or dehydrogenation) in the third oxide semiconductor film403 c may be performed, and oxygen may be supplied to the third oxidesemiconductor film 403 c using an oxygen gas.

The third oxide semiconductor film 403 c is deposited at a substratetemperature of room temperature using a target having an atomic ratio ofIn:Ga:Zn=1:3:2. The third oxide semiconductor film 403 c is depositedunder substantially the same deposition conditions as those of the firstoxide semiconductor film 403 a and the entire third oxide semiconductorfilm 403 c has substantially uniform film quality. The third oxidesemiconductor film 403 c has a thickness greater than or equal to 10 nmand less than or equal to 40 nm, preferably greater than or equal to 20nm and less than or equal to 30 nm. A cross-sectional view at this stageis illustrated in FIG. 4A.

Then, a conductive film is formed over the third oxide semiconductorfilm 403 c and processed to form the electrode layer 405 a and theelectrode layer 405 b (including a wiring formed with the same layer).Then, wet etching is performed using diluted hydrofluoric acid to reducethe thickness of part of the third oxide semiconductor film 403 c.

Next, an insulating film 407 is formed to cover the electrode layers 405a and 405 b and a stack 403 of oxide semiconductor films which isexposed. The insulating film 407 can be formed with a single layer or astack of layers using one or more of the following films formed by aplasma CVD method or a sputtering method: a silicon oxide film, agallium oxide film, an aluminum oxide film, a silicon nitride film, asilicon oxynitride film, an aluminum oxynitride film, a silicon nitrideoxide film, and the like. It is preferable that a first oxide insulatingfilm be formed to cover the stack 403 of oxide semiconductor films undera condition which causes little plasma damage in order to reduce plasmadamage, and that a second oxide insulating film be stacked thereoverunder a deposition condition which allows the film to contain a largeamount of oxygen. Note that it is preferable that an oxide insulatingfilm be formed as the insulating film 407 in contact with the stack 403of oxide semiconductor films because the oxide insulating film cansupply oxygen to the stack 403 of oxide semiconductor films. In thisembodiment, an oxide insulating film containing nitrogen is used as theinsulating film 407.

Next, oxygen is added to the insulating film 407 by an ion implantationmethod, an ion doping method, a plasma immersion ion implantationmethod, or the like. The timing of supply of oxygen to the stack 403 ofoxide semiconductor films is not particularly limited as long as it isafter the formation of the stack 403 of oxide semiconductor films. Thestep of introducing oxygen may be performed a plurality of times.

After the formation of the insulating film 407, heat treatment isperformed. The stack 403 of oxide semiconductor films is damaged bybeing exposed to plasma at the time of etching or deposition and thusincludes oxygen vacancies due to the damage; therefore, the heattreatment for repairing the damage to the oxide semiconductor isperformed, whereby oxygen is supplied and thus the oxygen vacancies arereduced. The temperature of the heat treatment is typically higher thanor equal to 200° C. and lower than or equal to 450° C. The heattreatment allows nitrogen contained in the oxide insulating filmcontaining nitrogen to be released. Note that the heat treatment caneliminate water, hydrogen, and the like from the oxide insulating filmcontaining nitrogen. In this embodiment, the heat treatment is performedin a mixed atmosphere of nitrogen and oxygen at 350° C. for 1 hour. Bythe heat treatment, hydrogen atoms and oxygen atoms included in theoxide semiconductor films are bonded in the oxide semiconductor films atan interface between the oxide semiconductor film and the oxideinsulating film containing nitrogen, in the oxide insulating filmcontaining nitrogen, or at the surface of the oxide insulating filmcontaining nitrogen to generate water molecules, and the water moleculesare desorbed from the oxide insulating film containing nitrogen. In theoxide semiconductor films, portions from which oxygen atoms are desorbedbecome oxygen vacancies; however, a large number of oxygen atoms whichare contained in the oxide insulating film containing nitrogen in excessof that of the stoichiometric composition move to the oxygen vacanciesto reduce the oxygen vacancies.

Further, it is preferable that the number of defects be small in theoxide insulating film containing nitrogen used as the insulating film407, and typically, the spin density of a signal at g=2.001 which is dueto dangling bonds of silicon by ESR measurement be lower than or equalto 3×10¹⁷ spins/cm³. This is because when the density of defects in theoxide insulating film containing nitrogen is high, oxygen may be bondedto the defect and the amount of oxygen that passes through the oxideinsulating film containing nitrogen is decreased.

In this manner, nitrogen, hydrogen, or water is desorbed from the oxidesemiconductor films by the heat treatment after the formation of theinsulating film 407, whereby the nitrogen, hydrogen, or water content ofthe films can be reduced to approximately one tenth.

Next, the protective insulating film 408 is formed over the insulatingfilm 407. An aluminum oxide film or a silicon nitride film is formed asthe protective insulating film 408. The protective insulating film 408has a role in preventing mixing of impurities such as hydrogen andmoisture from the outside.

Through the above manufacturing process, the transistor 411 of thisembodiment can be formed.

In the transistor described in this embodiment, the second oxidesemiconductor film 403 b which functions as a current path (channel) ofthe transistor is positioned between the first and third oxidesemiconductor films 403 a and 403 c which have lower carrier densitythan the second oxide semiconductor film 403 b. Accordingly, the channelcan be separated from the interface of the insulating film in contactwith the stack 403 of oxide semiconductor films, so that a buriedchannel can be obtained. Further, the second oxide semiconductor film403 b can contain as much oxygen as possible; therefore, the number ofgenerated oxygen vacancies is small and thus the reliability of thetransistor is improved.

Embodiment 2

In this embodiment, an example which is partly different from Embodiment1 is described below. The example of this embodiment differs fromEmbodiment 1 in the way to form the stack 403 of oxide semiconductorfilms, the way to supply oxygen, and the like.

The steps from formation of the transistor 311 using the first oxidesemiconductor material in the lower portion up to formation of thesecond interlayer insulating film 308, the barrier layer 310, and thethird wiring layer 309 are the same as those in Embodiment 1, and thusdetails of the steps are not described here.

A conductive film is formed over the barrier layer and selectivelyetched to form the fourth wiring layer 434 and the gate electrode 491.

Then, the insulating film 435 covering the gate electrode 491 is formedand planarized by CMP or the like. As the insulating film 435, an oxideinsulating film containing nitrogen is used.

Then, the first gate insulating film 402 a and the second gateinsulating film 402 b are formed. An oxide insulating film containingnitrogen is used as the first gate insulating film 402 a.

A 20-nm-thick silicon oxide film may be deposited as the second gateinsulating film 402 b by a plasma CVD method, and after the deposition,the silicon oxide film may be subjected to radical oxidation treatmentby microwave plasma treatment for repairing oxygen vacancies.

Next, with the use of a manufacturing apparatus illustrated in FIG. 11,a stack of oxide semiconductor films is deposited over the second gateinsulating film 402 b without exposure to the air

The first oxide semiconductor film 403 a, the second oxide semiconductorfilm 403 b, and the third oxide semiconductor film 403 c are formed.

A deposition temperature of each of the first, second, and third oxidesemiconductor films 403 a, 403 b, and 403 c is higher than or equal toroom temperature and lower than or equal to 550° C., preferably higherthan or equal to 200° C. and lower than 400° C. In order to make thesecond oxide semiconductor film 403 b a CAAC-OS film, the depositiontemperature is set to higher than or equal to 200° C. and lower than orequal to 550° C. In order to make the first and third oxidesemiconductor films 403 a and 403 c have a low degree of crystallinity,a deposition temperature of each of the first and third oxidesemiconductor films 403 a and 403 c is set to higher than or equal toroom temperature and lower than 200° C.

Then, selective etching is performed using a mask, so that theisland-shaped stack 403 of oxide semiconductor films is formed.

Then, a conductive film is formed over the third oxide semiconductorfilm 403 c and processed to form the electrode layer 405 a and theelectrode layer 405 b (including a wiring formed with the same layer).Then, wet etching is performed using diluted hydrofluoric acid to reducethe thickness of part of the third oxide semiconductor film 403 c.

Next, an insulating film 407 is formed to cover the electrode layers 405a and 405 b and the stack 403 of oxide semiconductor films which isexposed. The insulating film 407 preferably has a stacked-layerstructure. It is preferable that a first oxide insulating film be formedto cover the stack 403 of oxide semiconductor films under a conditionwhich causes little plasma damage in order to reduce plasma damage, andthat a second oxide insulating film be stacked thereover under adeposition condition which allows the film to contain a large amount ofoxygen.

Oxygen may be added to the insulating film 407 by an ion implantationmethod, an ion doping method, a plasma immersion ion implantationmethod, or the like. The timing of supply of oxygen to the stack 403 ofoxide semiconductor films is not particularly limited as long as it isafter the formation of the stack 403 of oxide semiconductor films. Thestep of introducing oxygen may be performed a plurality of times.

After formation of the insulating film 407, heat treatment is performedat a temperature higher than or equal to 350° C. and lower than or equalto 450° C. Oxygen contained in the insulating film 435, the first gateinsulating film 402 a, and the second gate insulating film 402 b issupplied to the stack 403 of oxide semiconductor films. Alternatively,the oxide insulating film containing nitrogen which is described inEmbodiment 1 may be used as the insulating film 407 and oxygen containedin the insulating film 407 may be supplied to the stack 403 of oxidesemiconductor films.

Next, the protective insulating film 408 is formed over the insulatingfilm 407. An aluminum oxide film or a silicon nitride film is formed asthe protective insulating film 408. The protective insulating film 408has a role in preventing mixing of impurities such as hydrogen andmoisture from the outside.

Through the above manufacturing process, as illustrated in FIG. 5, atransistor 412 of this embodiment can be formed over the transistor 311.

This embodiment can be freely combined with Embodiment 1.

Embodiment 3

As another example of a semiconductor device including the transistordescribed in Embodiment 1 or 2, a circuit diagram of a NOR circuit,which is a logic circuit, is illustrated in FIG. 6A. FIG. 6B illustratesa circuit diagram of a NAND circuit.

In the NOR circuit illustrated in FIG. 6A, p-channel transistors 801 and802 each have a structure similar to that of the transistor 311 in FIG.4B in that a single crystal silicon substrate is used for a channelformation region, and n-channel transistors 803 and 804 each have astructure similar to that of the transistor 411 in FIG. 4B and that ofthe transistor 412 in FIG. 5 in that an oxide semiconductor film is usedfor a channel formation region.

In the NOR circuit in FIG. 6A, conductive layers controlling electricalcharacteristics of the transistors may be provided to overlap with gateelectrode layers with oxide semiconductor films provided therebetween inthe transistors 803 and 804. By controlling the potential of theconductive layer to GND, for example, the threshold voltages of thetransistors 803 and 804 are increased, so that the transistors can benormally off.

In the NAND circuit in FIG. 6B, p-channel transistors 811 and 814 eachhave a structure similar to that of the transistor 311 in FIGS. 4A and4B, and n-channel transistors 812 and 813 each have a structure similarto that of the transistor 411 in FIG. 4B and that of the transistor 412in FIG. 5 in that an oxide semiconductor film is used for a channelformation region.

In the NAND circuit illustrated in FIG. 6B, conductive layerscontrolling electrical characteristics of the transistors are providedto overlap with gate electrode layers with oxide semiconductor filmsprovided therebetween in the transistors 812, and 813. By controllingthe potential of the conductive layer to GND, for example, the thresholdvoltages of the transistors 812 and 813 are increased, so that thetransistors can be normally off.

By applying a transistor including an oxide semiconductor for a channelformation region and having extremely small off-state current to thesemiconductor device in this embodiment, power consumption of thesemiconductor device can be sufficiently reduced.

A semiconductor device which is miniaturized, is highly integrated, andhas stable and excellent electrical characteristics by stackingsemiconductor elements including different semiconductor materials and amethod for manufacturing the semiconductor device can be provided.

The NOR circuit and the NAND circuit including the transistors describedin Embodiment 2 are described as examples in this embodiment; however,one embodiment of the present invention is not limited to the circuits,and an AND circuit, an OR circuit, or the like can be formed using thetransistors described in Embodiment 1 or 2. For example, a semiconductordevice (storage device) in which stored data can be held even when poweris not supplied and which has an unlimited number of times of writingwith the transistors described in Embodiment 1 or 2 can be manufactured.

Embodiment 4

In this embodiment, a central processing unit (CPU) at least part ofwhich includes one of the transistor 411 in FIG. 4B and the transistor412 in FIG. 5 is described as an example of a semiconductor device.

FIG. 7A is a block diagram illustrating a specific structure of a CPU.The CPU illustrated in FIG. 7A includes an arithmetic logic unit (ALU)1191, an ALU controller 1192, an instruction decoder 1193, an interruptcontroller 1194, a timing controller 1195, a register 1196, a registercontroller 1197, a bus interface (Bus UF) 1198, a rewritable ROM 1199,and an ROM interface (ROM I/F) 1189 over a substrate 1190. Asemiconductor substrate, an SOI substrate, a glass substrate, or thelike is used as the substrate 1190. The ROM 1199 and the ROM interface1189 may each be provided over a separate chip. Obviously, the CPUillustrated in FIG. 7A is only an example in which the structure issimplified, and an actual CPU has various structures depending on theapplication.

An instruction that is input to the CPU through the bus interface 1198is input to the instruction decoder 1193 and decoded therein, and then,input to the ALU controller 1192, the interrupt controller 1194, theregister controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the registercontroller 1197, and the timing controller 1195 conduct various controlsin accordance with the decoded instruction. Specifically, the ALUcontroller 1192 generates signals for controlling the operation of theALU 1191. While the CPU is executing a program, the interrupt controller1194 judges an interrupt request from an external input/output device ora peripheral circuit on the basis of its priority or a mask state, andprocesses the request. The register controller 1197 generates an addressof the register 1196, and reads/writes data from/to the register 1196 inaccordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operationtimings of the ALU 1191, the ALU controller 1192, the instructiondecoder 1193, the interrupt controller 1194, and the register controller1197. For example, the timing controller 1195 includes an internal clockgenerator for generating an internal clock signal CLK2 based on areference clock signal CLK1, and supplies the internal clock signal CLK2to the above circuits.

In the CPU illustrated in FIG. 7A, a memory cell is provided in theregister 1196.

In the CPU illustrated in FIG. 7A, the register controller 1197 selectsoperation of holding data in the register 1196 in accordance with aninstruction from the ALU 1191. That is, the register controller 1197selects whether data is held by a flip-flop or by a capacitor in thememory cell included in the register 1196. When data holding by theflip-flop is selected, a power supply voltage is supplied to the memorycell in the register 1196. When data holding by the capacitor isselected, the data is rewritten in the capacitor, and supply of powersupply voltage to the memory cell in the register 1196 can be stopped.

The power supply can be stopped by providing a switching element betweena memory cell group and a node to which a power supply potential VDD ora power supply potential VSS is supplied, as illustrated in FIG. 7B orFIG. 7C. Circuits illustrated in FIGS. 7B and 7C are described below.

FIGS. 7B and 7C each illustrate an example of a memory circuitconfiguration in which one of the transistor 411 in FIG. 4B and thetransistor 412 in FIG. 5 is used as a switching element which controlssupply of a power supply potential to a memory cell.

The memory device illustrated in FIG. 7B includes a switching element1141 and a memory cell group 1143 including a plurality of memory cells1142. Each of the memory cells 1142 included in the memory cell group1143 is supplied with the high-level power supply potential VDD via theswitching element 1141. Further, each of the memory cells 1142 includedin the memory cell group 1143 is supplied with a potential of a signalIN and the low-level power supply potential VSS.

In FIG. 7B, one of the transistor 411 in FIG. 4B and the transistor 412in FIG. 5 is used as the switching element 1141, and the switching ofthe transistor is controlled by a signal Sig A supplied to a gateelectrode thereof.

Note that FIG. 7B illustrates the structure in which the switchingelement 1141 includes only one transistor; however, without limitationthereto, the switching element 1141 may include a plurality oftransistors. In the case where the switching element 1141 includes aplurality of transistors which serves as switching elements, theplurality of transistors may be connected to each other in parallel, inseries, or in combination of parallel connection and series connection.

Although the switching element 1141 controls the supply of thehigh-level power supply potential VDD to each of the memory cells 1142included in the memory cell group 1143 in FIG. 7B, the switching element1141 may control the supply of the low-level power supply potential VSS.

In FIG. 7C, an example of a memory device in which each of the memorycells 1142 included in the memory cell group 1143 is supplied with thelow-level power supply potential VSS via the switching element 1141 isillustrated. The supply of the low-level power supply potential VSS toeach of the memory cells 1142 included in the memory cell group 1143 canbe controlled by the switching element 1141.

When a switching element is provided between a memory cell group and anode to which the power supply potential VDD or the power supplypotential VSS is supplied, data can be held even in the case where anoperation of a CPU is temporarily stopped and the supply of the powersupply voltage is stopped; accordingly, power consumption can bereduced. Specifically, for example, while a user of a personal computerdoes not input data to an input device such as a keyboard, the operationof the CPU can be stopped, so that the power consumption can be reduced.

Although the CPU is given as an example, the transistor can also beapplied to an LSI such as a digital signal processor (DSP), a customLSI, or a field programmable gate array (FPGA).

The methods and structures described in this embodiment can be combinedas appropriate with any of the methods and structures described in theother embodiments.

Embodiment 5

In this embodiment, a semiconductor device that is one embodiment of thepresent invention is described using a liquid crystal display device asan example.

FIG. 8A illustrates a structural example of a semiconductor device. Thesemiconductor device in FIG. 8A includes a pixel portion 100, a scanline driver circuit 104, a signal line driver circuit 106, m scan lines107 which are arranged in parallel or substantially in parallel andwhose potentials are controlled by the scan line driver circuit 104, andn signal lines 109 which are arranged in parallel or substantially inparallel and whose potentials are controlled by the signal line drivercircuit 106. Further, the pixel portion 100 includes a plurality ofpixels 101 arranged in a matrix. Furthermore, capacitor lines 115arranged in parallel or substantially in parallel are provided along thescan lines 107. Note that the capacitor lines 115 may be arranged inparallel or substantially in parallel along the signal lines 109.

Each scan line 107 is electrically connected to the n pixels 101 in thecorresponding row among the pixels 101 arranged in m rows and n columnsin the pixel portion 100. Each signal line 109 is electrically connectedto the m pixels 101 in the corresponding column among the pixels 101arranged in m rows and n columns. Note that m and n are each an integerof 1 or more. Each capacitor line 115 is electrically connected to the npixels 101 in the corresponding row among the pixels 101 arranged in mrows and n columns. Note that in the case where the capacitor lines 115are arranged in parallel or substantially in parallel along the signallines 109, each capacitor line 115 is electrically connected to the mpixels 101 in the corresponding column among the pixels 101 arranged inm rows and n columns.

FIG. 8B is an example of a circuit diagram of the pixel 101 included inthe semiconductor device illustrated in FIG. 8A. The pixel 101 in FIG.8B includes a transistor 103 a gate electrode of which is electricallyconnected to the scan line 107 and a source electrode of which iselectrically connected to the signal line 109, a capacitor 105 oneelectrode of which is electrically connected to a drain electrode of thetransistor 103 and the other electrode of which is electricallyconnected to the capacitor line 115 which supplies a constant potential,and a liquid crystal element 108. A pixel electrode of the liquidcrystal element 108 is electrically connected to the drain electrode ofthe transistor 103 and the one electrode of the capacitor 105, and anelectrode (counter electrode) facing the pixel electrode is electricallyconnected to a wiring which supplies a counter potential.

The liquid crystal element 108 is an element which controls transmissionof light by an optical modulation action of liquid crystal which ispositioned between a substrate provided with the transistor 103 and thepixel electrode and a substrate provided with the counter electrode. Theoptical modulation action of liquid crystal is controlled by an electricfield applied to the liquid crystal (including a horizontal electricfield, a vertical electric field, and a diagonal electric field).

Next, a specific structural example of the pixel 101 of the liquidcrystal display device will be described. FIG. 9 is a top view of thepixel 101. Note that in FIG. 9, the counter electrode and the liquidcrystal element are omitted.

In FIG. 9, the scan line 107 is provided so as to extend in thedirection perpendicular or substantially perpendicular to the signalline 109 (in the horizontal direction in FIG. 9). The signal line 109 isprovided so as to extend in the direction perpendicular or substantiallyperpendicular to the scan line 107 (in the vertical direction in FIG.9). The capacitor line 115 is provided so as to extend in the directionparallel with the scan line 107. The scan line 107 and the capacitorline 115 are electrically connected to the scan line driver circuit 104(see FIG. 8A), and the signal line 109 is electrically connected to thesignal line driver circuit 106 (see FIG. 8A).

The transistor 103 is provided in a region where the scan line 107 andthe signal line 109 cross each other. The transistor 103 includes atleast a stack 111 of oxide semiconductor films including a channelformation region, a gate electrode, a gate insulating film (notillustrated in FIG. 9), a source electrode, and a drain electrode.

In the stack 111 of the oxide semiconductor films, as illustrated inFIG. 10, a first oxide semiconductor film 111 a, a second oxidesemiconductor film 111 b, and a third oxide semiconductor film 111 c arestacked in this order. Materials of the first to third oxidesemiconductor films 111 a, 111 b, and 111 c are selected as appropriateso that a well-shaped structure in which the bottom of the conductionband in the second oxide semiconductor film 111 b is deeper than thebottoms of the conduction band in the first and third oxidesemiconductor films 111 a and 111 c is obtained. In this embodiment, thefirst and third oxide semiconductor films 111 a and 111 c are formedusing a target having an atomic ratio of In:Ga:Zn=1:3:2, and the secondoxide semiconductor film 111 b is formed using a target having an atomicratio of In:Ga:Zn=1:1:1. The stack 111 of oxide semiconductor filmsenables formation of a buried channel and a reduction in oxygenvacancies, thereby improving the reliability of the transistor 103.

Further, when the stack 111 of oxide semiconductor films is deposited orsubjected to heat treatment under an appropriate condition, theoff-state current of the transistor can be significantly reduced;therefore, the power consumption of the semiconductor device can bereduced.

The scan line 107 also functions as a gate electrode of the transistor103, and the signal line 109 also functions as a source electrode of thetransistor 103. A conductive film 113 functions as a drain electrode ofthe transistor 103 and is electrically connected to a pixel electrode121 through an opening 117. Note that pixel electrode 121 is illustratedwithout hatching in FIG. 9. Further, the scan line 107 is represented asit is even when it indicates the gate electrode of the transistor, andthe signal line 109 is represented as it is even when it indicates thesource electrode of the transistor.

The capacitor 105 is provided in a region which is in the pixel 101 andsurrounded by the capacitor lines 115 and the signal lines 109. Thecapacitor 105 is electrically connected to the capacitor line 115through a conductive film 125 provided in and over an opening 123. Thecapacitor 105 includes a stack 119 of oxide semiconductor films, thepixel electrode 121, and an insulating film (not illustrated in FIG. 9)which is formed as a dielectric film over the transistor 103. The oxidesemiconductor film 119, the pixel electrode 121, and the dielectric filmtransmit light; accordingly, the capacitor 105 transmits light.

Thanks to the light-transmitting property of the stack 119 of oxidesemiconductor films, the capacitor 105 can be formed large (in a largearea) in the pixel 101. For this reason, the semiconductor device canhave charge capacity increased while the aperture ratio is not reducedor is improved. Further, by improving the aperture ratio, asemiconductor device having high display quality can be obtained.

Here, the characteristics of a transistor including an oxidesemiconductor will be described. The transistor including an oxidesemiconductor is an n-channel transistor. Further, oxygen vacancies inthe oxide semiconductor might generate carriers, which might degrade theelectrical characteristics and reliability of the transistor. Forexample, in some cases, the threshold voltage of the transistor isshifted in the negative direction, and drain current flows when the gatevoltage is 0 V. The characteristics of a transistor in which draincurrent flows when the gate voltage is 0 V are referred to asnormally-on characteristics, whereas the characteristics of a transistorin which substantially no drain current flows when the gate voltage is 0V are referred to as normally-off characteristics.

It is preferable that defects in the stack 111 of oxide semiconductorfilms, typically, oxygen vacancies be reduced as much as possible. Forexample, it is preferable that the spin density of the stack 111 ofoxide semiconductor films (the density of defects in the oxidesemiconductor films) at a g-value of 1.93 in electron spin resonancespectroscopy in which a magnetic field is applied in parallel with thefilm surface be reduced to lower than or equal to the lower detectionlimit of measurement equipment. When the defects typified by oxygenvacancies in the oxide semiconductor films are reduced as much aspossible, the transistor 103 can be prevented from being normally on,leading to improvements in the electrical characteristics andreliability of a semiconductor device.

It is preferable that impurities (e.g., hydrogen, moisture, and elementsbelonging to Group 14) contained in the stack 111 of oxide semiconductorfilms be reduced as much as possible, and when the oxide semiconductorfilms are highly purified to be i-type oxide semiconductor films, thetransistor 103 can be prevented from being normally on; as a result, theoff-state current of the transistor 103 can be significantly reduced.Therefore, a semiconductor device having favorable electricalcharacteristics can be manufactured. Further, a highly reliablesemiconductor device can be manufactured.

Next, FIG. 10 is a cross-sectional view taken along dashed-dotted linesA1-A2 and B1-B2 in FIG. 9.

A cross-sectional structure of the pixel 101 of the liquid crystaldisplay device is as follows. The liquid crystal display device includesan element portion over a substrate 102, an element portion on asubstrate 150, and a liquid crystal layer sandwiched between the twoelement portions.

First, the structure of the element portion formed over the substrate102 is described. The scan line 107 functioning as the gate electrode ofthe transistor 103 and the capacitor line 115 over the same surface asthe scan line 107 are provided over the substrate 102. A gate insulatingfilm 127 is provided over the scan line 107 and the capacitor line 115.The stack 111 of oxide semiconductor films is provided over a portion ofthe gate insulating film 127 which overlaps with the scan line 107, andthe stack 119 of oxide semiconductor films is provided over the gateinsulating film 127. The signal line 109 functioning as the sourceelectrode of the transistor 103 and the conductive film 113 functioningas the drain electrode of the transistor 103 are provided over the stack111 of oxide semiconductor films and the gate insulating film 127. Anopening 123 reaching the capacitor line 115 is formed in the gateinsulating film 127, and the conductive film 125 is provided over theopening 123, the gate insulating film 127, and the stack 119 of oxidesemiconductor films. An insulating film 129, an insulating film 131, andan insulating film 132 functioning as protective insulating films of thetransistor 103 are provided over the gate insulating film 127, thesignal line 109, the stack 111 of oxide semiconductor films, theconductive film 113, the conductive film 125, and the stack 119 of oxidesemiconductor films. The opening 117 reaching the conductive film 113 isformed in the insulating film 129, the insulating film 131, and theinsulating film 132, and the pixel electrode 121 is provided over theopening 117 and the insulating film 132. An insulating film 158functioning as an alignment film is provided over the pixel electrode121 and the insulating film 132. Note that a base insulating film may beprovided between the substrate 102, and the scan line 107, the capacitorline 115, and the gate insulating film 127.

In the capacitor 105 of this structure, the stack 119 of oxidesemiconductor films formed in the same step as the stack 111 of oxidesemiconductor films serves as one of a pair of electrodes, the pixelelectrode 121 serves as the other of the pair of electrodes, and theinsulating film 129, the insulating film 131, and the insulating film132 serve as dielectric films provided between the pair of electrodes.

The details of the components of the above structure are describedbelow.

Although there is no particular limitation on a material and the like ofthe substrate 102, it is necessary that the substrate have heatresistance high enough to withstand at least heat treatment performed ina manufacturing process of a semiconductor device. Examples of thesubstrate are a glass substrate, a ceramic substrate, and a plasticsubstrate, and as the glass substrate, an alkali-free glass substratesuch as a barium borosilicate glass substrate, an aluminoborosilicateglass substrate, or an aluminosilicate glass substrate is preferablyused. As the substrate 102, a quartz substrate, a sapphire substrate, orthe like can be used.

The scan line 107 and the capacitor line 115 are formed to have asingle-layer structure or a stacked-layer structure using any of metalmaterials such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum(Ta), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), orscandium (Sc), or an alloy material which contains any of thesematerials as its main component.

Examples of the scan line 107 and the capacitor line 115 are asingle-layer structure using aluminum containing silicon, a two-layerstructure in which titanium is stacked over aluminum, a two-layerstructure in which titanium is stacked over titanium nitride, atwo-layer structure in which tungsten is stacked over titanium nitride,a two-layer structure in which tungsten is stacked over tantalumnitride, a two-layer structure in which copper is stacked over Cu—Mg—Alalloy, and a three-layer structure in which titanium nitride, copper,and tungsten are stacked in this order.

As a material of the scan line 107 and the capacitor line 115, alight-transmitting conductive material which can be used for the pixelelectrode 121 can be used.

The scan line 107 and the capacitor line 115 are preferably formed usingaluminum or copper, which are low resistance materials. With the use ofaluminum or copper, signal delay is reduced, so that higher imagequality can be achieved. Note that aluminum has low heat resistance, andthus a defect due to hillocks, whiskers, or migration is easilygenerated. To prevent migration of aluminum, a layer of a metal materialhaving a higher melting point than aluminum, such as molybdenum,titanium, or tungsten, is preferably stacked over an aluminum layer.Also in the case where copper is used, in order to prevent a defect dueto migration and diffusion of copper elements, a layer of a metalmaterial having a higher melting point than copper, such as molybdenum,titanium, or tungsten, is preferably stacked over a copper layer.

The gate insulating film 127 is formed to have a single-layer structureor a stacked-layer structure using, for example, any of insulatingmaterials such as silicon oxide, silicon oxynitride, silicon nitrideoxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide,and a Ga—Zn-based metal oxide. In order to improve the characteristicsof the interface between the gate insulating film 127 and the stack 111of oxide semiconductor films, a region in the gate insulating film 127which is in contact with at least the stack 111 of oxide semiconductorfilms is preferably formed using an oxide insulating film.

Further, it is possible to prevent outward diffusion of oxygen from thestack 111 of oxide semiconductor films and entry of hydrogen, water, orthe like into the stack 111 of oxide semiconductor films from theoutside by providing an insulating film having a barrier propertyagainst oxygen, hydrogen, water, and the like as the gate insulatingfilm 127. Examples of the insulating film having a barrier propertyagainst oxygen, hydrogen, water, and the like are an aluminum oxidefilm, an aluminum oxynitride film, a gallium oxide film, a galliumoxynitride film, an yttrium oxide film, an yttrium oxynitride film, ahafnium oxide film, a hafnium oxynitride film, and a silicon nitridefilm.

The gate insulating film 127 may be formed using a high-k material suchas hafnium silicate (HfSiO_(x)), hafnium silicate containing nitrogen(HfSi_(x)O_(y)N_(z)), hafnium aluminate containing nitrogen(HfAl_(x)O_(y)N_(z)), hafnium oxide, or yttrium oxide, in which casegate leakage current of the transistor 103 can be reduced.

The gate insulating film 127 preferably has the following stacked-layerstructure. It is preferable that a silicon nitride film having fewerdefects be provided as a first silicon nitride film, a silicon nitridefilm from which less hydrogen and ammonia are released be provided as asecond silicon nitride film over the first silicon nitride film, and anyof the oxide insulating films listed as those used for the gateinsulating film 127 be provided over the second silicon nitride film.

As the second silicon nitride film, a nitride insulating film whichreleases hydrogen molecules less than 5×10²¹ molecules/cm³, preferablyless than or equal to 3×10²¹ molecules/cm³, more preferably less than orequal to 1×10²¹ molecules/cm³, and ammonia molecules less than 1×10²²molecules/cm³, preferably less than or equal to 5×10²¹ molecules/cm³,more preferably less than or equal to 1×10²¹ molecules/cm³ by thermaldesorption spectroscopy is preferably used. The first silicon nitridefilm and the second silicon nitride film are used as part of the gateinsulating film 127, whereby a gate insulating film which has fewerdefects and from which less hydrogen and ammonia are released can beformed as the gate insulating film 127. Thus, the amount of hydrogen andnitrogen contained in the gate insulating film 127 which enter the stack111 of oxide semiconductor films can be reduced.

In the case where the trap level (also referred to as interface level)is present at the interface between the stack 111 of oxide semiconductorfilms and the gate insulating film or in the gate insulating film in thetransistor including an oxide semiconductor, a shift of the thresholdvoltage of the transistor, typically, a shift of the threshold voltagein the negative direction, and an increase in the subthreshold swing (Svalue) showing a gate voltage needed for changing the drain current byan order of magnitude when the transistor is turned on are caused. As aresult, there is a problem in that electrical characteristics vary amongtransistors. Therefore, the use of a silicon nitride film having fewerdefects as a gate insulating film and provision of an oxide insulatingfilm in contact with the first oxide semiconductor film 111 a can reducea shift of the threshold voltage in the negative direction and minimizean increase in S value.

The thickness of the gate insulating film 127 is greater than or equalto 5 nm and less than or equal to 400 nm, preferably greater than orequal to 10 nm and less than or equal to 300 nm, further preferablygreater than or equal to 50 nm and less than or equal to 250 nm.

In this embodiment, the first and third oxide semiconductor films 111 aand 111 c are films with a low degree of crystallinity, and the secondoxide semiconductor film 111 b has a crystalline structure. After a filmwith a low degree of crystallinity is formed as the first oxidesemiconductor film 111 a and the second oxide semiconductor film 111 bis deposited, heat treatment (at a temperature higher than or equal to200° C. and lower than or equal to 550° C.) is performed, and then thethird oxide semiconductor film 111 c is formed. This process ispreferably performed without exposure to the air, using a manufacturingapparatus illustrated in FIG. 11. Further, also in the stack 119 ofoxide semiconductor films which is formed through a process similar tothat of the stack 111 of oxide semiconductor films, the first and thirdoxide semiconductor films are films with a low degree of crystallinityand the second oxide semiconductor film is a film having a crystallinestructure with a high degree of crystallinity and is a CAAC-OS film. Thethickness of the stack 111 of oxide semiconductor films is greater thanor equal to 1 nm and less than or equal to 100 nm, preferably greaterthan or equal to 1 nm and less than or equal to 50 nm, furtherpreferably greater than or equal to 3 nm and less than or equal to 20nm.

When the buried channel is formed in the transistor 103, few oxygenvacancies are generated and the reliability of the transistor isimproved.

An oxide semiconductor which can be used for the stack 111 of oxidesemiconductor films and the stack 119 of oxide semiconductor films hasan energy gap of greater than or equal to 2 eV, preferably greater thanor equal to 2.5 eV, more preferably greater than or equal to 3 eV. Theuse of such an oxide semiconductor having a wide energy gap can reducethe off-state current of the transistor 103.

The signal line 109 functioning as the source electrode of thetransistor 103, the conductive film 113 functioning as the drainelectrode of the transistor 103, and the conductive film 125electrically connecting the stack 119 of oxide semiconductor films andthe capacitor line 115 in the capacitor 105 are formed to have asingle-layer structure or a stacked-layer structure using a materialwhich can be used for the scan line 107 and the capacitor line 115.

The insulating films 129, 131, and 132 functioning as the protectiveinsulating films of the transistor 103 and the dielectric films in thecapacitor 105 are insulating films each formed using a material whichcan be used for the gate insulating film 127. It is particularlypreferable that the insulating films 129 and 131 be oxide insulatingfilms and the insulating film 132 be a nitride insulating film. Furtherthe use of a nitride insulating film as the insulating film 132 cansuppress entry of impurities such as hydrogen and water into thetransistor 103 (in particular, the second oxide semiconductor film 111b) from the outside. Note that the insulating film 129 is notnecessarily provided.

Further, an oxide insulating film in which the oxygen content is higherthan that in the stoichiometric composition is preferably used as one ofor both the insulating film 129 and the insulating film 131. In thatcase, oxygen can be prevented from being released from the oxidesemiconductor film, and the oxygen contained in an oxygen excess regioncan enter the oxide semiconductor film to reduce oxygen vacancies. Forexample, when an oxide insulating film having the following feature isused, oxygen vacancies in the oxide semiconductor film can be reduced.The feature of the oxide insulating film is that the number of oxygenmolecules released from the oxide insulating film is greater than orequal to 1.0×10¹⁸ molecules/cm³ when measured by thermal desorptionspectroscopy (hereinafter referred to as TDS spectroscopy). Note that anoxide insulating film partly including a region in which the oxygencontent is higher than that in the stoichiometric composition (oxygenexcess region) may be used as one of or both the insulating film 129 andthe insulating film 131. When such an oxygen excess region is present ina region overlapping with at least the stack 111 of semiconductor films,oxygen is prevented from being released from the oxide semiconductorfilm and the oxygen contained in the oxygen excess region can enter theoxide semiconductor film to reduce oxygen vacancies.

In the case where the insulating film 131 is an oxide insulating film inwhich the oxygen content is higher than that in the stoichiometriccomposition, the insulating film 129 is preferably an oxide insulatingfilm through which oxygen penetrates. Oxygen which enters the insulatingfilm 129 from the outside does not completely penetrate through theinsulating film 129 to be released and part thereof remains in theinsulating film 129. Further, there is oxygen which is contained in theinsulating film 129 from the first and is released from the insulatingfilm 129 to the outside. Thus, the insulating film 129 preferably has ahigh coefficient of diffusion of oxygen.

Since the insulating film 129 is in contact with the third oxidesemiconductor film 111 c, the insulating film 129 is preferably an oxideinsulating film through which oxygen penetrates and which has a lowinterface state with the third oxide semiconductor film 111 c. Forexample, the insulating film 129 is preferably an oxide insulating filmhaving a lower defect density than the insulating film 131.Specifically, the spin density of the oxide insulating film at a g-valueof 2.001 (E′-center) measured by electron spin resonance spectroscopy islower than or equal to 3.0×10¹⁷ spins/cm³, preferably lower than orequal to 5.0×10¹⁶ spins/cm³. The spin density at a g-value of 2.001measured by electron spin resonance spectroscopy corresponds to thenumber of dangling bonds in the insulating film 129.

The insulating film 129 can have a thickness of greater than or equal to5 nm and less than or equal to 150 nm, preferably greater than or equalto 5 nm and less than or equal to 50 nm, more preferably greater than orequal to 10 nm and less than or equal to 30 nm. The insulating film 131can have a thickness of greater than or equal to 30 nm and less than orequal to 500 nm, preferably greater than or equal to 150 nm and lessthan or equal to 400 nm.

In the case where a nitride insulating film is used as the insulatingfilm 132, an insulating film having a barrier property against nitrogenis preferably used as one of or both the insulating film 129 and theinsulating film 131. For example, a dense oxide insulating film has abarrier property against nitrogen. Specifically, an oxide insulatingfilm which can be etched at a rate of less than or equal to 10 nm perminute when the temperature is 25° C. and 0.5 wt % of fluoric acid isused is preferably used.

In the case where an oxide insulating film containing nitrogen, such asa silicon oxynitride film or a silicon nitride oxide film, is used asone of or both the insulating film 129 and the insulating film 131, thenitrogen concentration measured by SIMS is greater than or equal to thelower limit of measurement by SIMS and less than 3×10²⁰ atoms/cm³,preferably greater than or equal to 1×10¹⁸ atoms/cm³ and less than orequal to 1×10²⁰ atoms/cm³. In that case, the amount of nitrogen whichenters the stack 111 of oxide semiconductor films included in thetransistor 103 can be reduced and the number of defects in thenitrogen-containing oxide insulating film itself can be reduced.

As the insulating film 132, a nitride insulating film where the hydrogencontent is low may be provided. The nitride insulating film is asfollows, for example: the number of hydrogen molecules released from thenitride insulating film is less than 5.0×10²¹ molecules/cm³, preferablyless than 3.0×10²¹ molecules/cm³, more preferably less than 1.0×10²¹molecules/cm³ when measured by TDS spectroscopy.

The insulating film 132 has a thickness large enough to prevent entry ofimpurities such as hydrogen and water from the outside. For example, thethickness can be greater than or equal to 50 nm and less than or equalto 200 nm, preferably greater than or equal to 50 nm and less than orequal to 150 nm, more preferably greater than or equal to 50 nm and lessthan or equal to 100 nm.

The pixel electrode 121 can be provided using a light-transmittingconductive material such as indium tin oxide, indium oxide containingtungsten oxide, indium zinc oxide containing tungsten oxide, indiumoxide containing titanium oxide, indium tin oxide containing titaniumoxide, indium zinc oxide, or indium tin oxide to which silicon oxide isadded. Further, the scan line driver circuit 104 and the signal linedriver circuit 106 illustrated in FIG. 8A can be formed over the samesubstrate. In the case where a transistor including an oxidesemiconductor film is formed as a transistor which is provided in thescan line driver circuit 104 or the signal line driver circuit 106, anelectrode functioning as a back gate may be formed over the oxidesemiconductor film in the same step as formation of the pixel electrode121. When the electrode functioning as a back gate is provided over thetransistor in the scan line driver circuit 104 or the signal line drivercircuit 106 to overlap with the transistor, the reliability of thetransistor can be improved.

Next, the structure of the element portion provided over the substrate150 is described. A light-blocking film 152 is provided over thesubstrate 150, an electrode (a counter electrode 154) is provided overthe light-blocking film 152 so as to face the pixel electrode 121, andan insulating film 156 which functions as an alignment film is providedover the counter electrode 154.

The light-blocking film 152 prevents the transistor 103 from beingirradiated with backlight or light from the outside. The light-blockingfilm 152 can be formed using a material such as a metal or an organicresin including a pigment and may be provided in a region outside thepixel portion 100, such as over the scan line driver circuit 104 andover the signal line driver circuit 106 (see FIGS. 8A to 8C), as well asover the transistor 103 in the pixel 101.

Note that a coloring film which transmits light with a predeterminedwavelength may be provided between the light-blocking films 152 adjacentto each other. Further, an overcoat film may be provided between thecounter electrode 154, and the light-blocking films 152 and the coloringfilm.

The counter electrode 154 is formed using any of the light-transmittingconductive materials given as those used for the pixel electrode 121 asappropriate.

The liquid crystal element 108 includes the pixel electrode 121, thecounter electrode 154, and a liquid crystal layer 160. The liquidcrystal layer 160 is sandwiched between the insulating film 158 which isprovided in the element portion over the substrate 102 and functions asan alignment film and the insulating film 156 which is provided in theelement portion over the substrate 150 and functions as an alignmentfilm. Further, the pixel electrode 121 overlaps with the counterelectrode 154 with the liquid crystal layer 160 interposed therebetween.

Here, connection of the components included in the pixel 101 describedin this embodiment is described with reference to the circuit diagram inFIG. 8C and the cross-sectional view in FIG. 10.

FIG. 8C is an example of a detailed circuit diagram of the pixel 101included in the semiconductor device illustrated in FIG. 8A. Asillustrated in FIG. 8C and FIG. 10, the transistor 103 includes the scanline 107 including the gate electrode 107 a, the signal line 109including the source electrode 109 a, and the conductive film 113including the drain electrode 113 a.

In the capacitor 105, the stack 119 of oxide semiconductor filmsconnected to the capacitor line 115 through the conductive film 125functions as one electrode; the pixel electrode 121 connected to theconductive film 113 including the drain electrode 113 a functions as theother electrode; and the insulating films 129, 131, and 132 providedbetween the oxide semiconductor film 119 and the pixel electrode 121function as dielectric films.

The liquid crystal element 108 includes the pixel electrode 121, thecounter electrode 154, and the liquid crystal layer 160 provided betweenthe pixel electrode 121 and the counter electrode 154.

Despite having the same structure as the stack 111 of oxidesemiconductor films, the stack 119 of oxide semiconductor films in thecapacitor 105 functions as the electrode of the capacitor 105. This isbecause the pixel electrode 121 can function as a gate electrode, theinsulating films 129, 131, and 132 can function as gate insulatingfilms, and a capacitor line 115 can function as a source electrode or adrain electrode, so that the capacitor 105 can be operated in a mannersimilar to that of a transistor and the stack 119 of oxide semiconductorfilms can be made to be in a conductive state. In other words, thecapacitor 105 can serve as a MOS capacitor, the stack 119 of oxidesemiconductor films can be made to be in a conductive state so that thestack 119 of oxide semiconductor films can function as one electrode ofthe capacitor by controlling a potential to be supplied to the capacitorline 115. In this case, the potential to be supplied to the capacitorline 115 is set as follows. The potential of the pixel electrode 121 ischanged in the positive direction and the negative direction in order tooperate the liquid crystal element 108 (see FIG. 8C). The potential ofthe capacitor line 115 needs to be constantly lower than the potentialto be supplied to the pixel electrode 121 by the threshold voltage ofthe capacitor 105 (MOS capacitor) or more in order that the capacitor105 (MOS capacitor) be constantly in a conductive state. In other words,since the stack 119 of oxide semiconductor films has the same structureas the stack 111 of oxide semiconductor films, the potential of thecapacitor line 115 should be lower than the potential to be supplied tothe pixel electrode 121 by the threshold voltage of the transistor 103or more. In such a manner, a channel is formed; thus, the capacitor 105(MOS capacitor) can be made to be in a conductive state constantly.

When an oxide insulating film through which oxygen penetrates and whichhas fewer interface states between the third oxide semiconductor film111 c and the oxide insulating film is used as the insulating film 129over the stack 111 of oxide semiconductor films and the stack 119 ofoxide semiconductor films, and an oxide insulating film which includesan oxygen excess region or an oxide insulating film in which the oxygencontent is higher than that in the stoichiometric composition is used asthe insulating film 131, oxygen can be easily supplied to the stack 111of oxide semiconductor films, the release of oxygen from the stack 111of oxide semiconductor films can be prevented, and the oxygen containedin the insulating film 131 can enter the stack 111 of oxidesemiconductor films to reduce oxygen vacancies in the stack 111 of oxidesemiconductor films. Thus, the transistor 103 can be prevented frombeing normally on and a potential to be supplied to the capacitor line115 can be controlled so that the capacitor 105 (MOS capacitor) can beconstantly in a conductive state; thus, the semiconductor device canhave favorable electrical characteristics and high reliability.

The use of a nitride insulating film as the insulating film 132 over theinsulating film 131 can suppress entry of impurities such as hydrogenand water into the stack 111 of oxide semiconductor films and the stack119 of oxide semiconductor films from the outside. Moreover, the use ofa nitride insulating film with a low hydrogen content as the insulatingfilm 132 can minimize variations in electrical characteristics of thetransistor 103 and the capacitor 105 (MOS capacitor).

Further, the capacitor 105 can be formed large (in a large area) in thepixel 101. Therefore, a semiconductor device in which the aperture ratiois not reduced or is improved and the charge capacitance is increasedcan be obtained. Further, with the increased aperture ratio, thesemiconductor device can have favorable display quality.

Embodiment 6

A semiconductor device disclosed in this specification can be applied toa variety of electronic appliances (including game machines). Asemiconductor device disclosed in this specification can be applied to avariety of electronic appliances (including game machines). Examples ofthe electronic appliances include display devices of televisions,monitors, and the like, lighting devices, desktop personal computers andlaptop personal computers, word processors, image reproduction deviceswhich reproduce still images or moving images stored in recording mediasuch as digital versatile discs (DVDs), portable compact disc (CD)players, radio receivers, tape recorders, headphone stereos, stereos,cordless phone handsets, transceivers, mobile phones, car phones,portable game machines, calculators, portable information terminals,electronic notebooks, e-book readers, electronic translators, audioinput devices, cameras such as still cameras and video cameras, electricshavers, high-frequency heating appliances such as microwave ovens,electric rice cookers, electric washing machines, electric vacuumcleaners, air-conditioning systems such as air conditioners,dishwashers, dish dryers, clothes dryers, futon dryers, electricrefrigerators, electric freezers, electric refrigerator-freezers,freezers for preserving DNA, smoke detectors, radiation counters, andmedical equipment such as dialyzers. Further, the examples includeindustrial equipment such as guide lights, traffic lights, beltconveyors, elevators, escalators, industrial robots, and power storagesystems. In addition, oil engines, moving objects driven by electricmotors using power from the non-aqueous secondary batteries, and thelike are also included in the category of electronic appliances.Examples of the moving objects include electric vehicles (EV), hybridelectric vehicles (HEV) which include both an internal-combustion engineand a motor, plug-in hybrid electric vehicles (PHEV), tracked vehiclesin which caterpillar tracks are substituted for wheels of thesevehicles, motorized bicycles including motor-assisted bicycles,motorcycles, electric wheelchairs, golf carts, boats or ships,submarines, helicopters, aircrafts, rockets, artificial satellites,space probes, planetary probes, spacecrafts, and the like. Specificexamples of these electronic appliances are shown in FIGS. 12A to 12Cand FIGS. 13A to 13C.

FIGS. 12A and 12B illustrate a tablet terminal that can be folded. InFIG. 12A, the tablet terminal is opened, and includes a housing 9630, adisplay portion 9631 a, a display portion 9631 b, a display-modeswitching button 9034, a power button 9035, a power-saving-modeswitching button 9036, a clip 9033, and an operation button 9038.

A CPU for performing image processing or arithmetic processing is usedin the portable device illustrated in FIGS. 12A and 12B. As the CPU, theCPU described in Embodiment 4 can be used, in which case the CPUdescribed in Embodiment 4 is used, power consumption of the portabledevice can be reduced.

The display device described in Embodiment 5 can be used for the displayportions 9631 a and 9631 b. The use of the display device leads to animprovement in reliability.

A touch panel area 9632 a can be provided in a part of the displayportion 9631 a, in which data can be input by touching displayedoperation keys 9638. Note that FIG. 12A shows, as an example, that halfof the area of the display portion 9631 a has only a display functionand the other half of the area has a touch panel function. However, thestructure of the display portion 9631 a is not limited to this, and allthe area of the display portion 9631 a may have a touch panel function.For example, all the area of the display portion 9631 a can displaykeyboard buttons and serve as a touch panel while the display portion9631 b can be used as a display screen.

Like the display portion 9631 a, part of the display portion 9631 b canbe a touch panel area 9632 b. When a finger, a stylus, or the liketouches the place where a button 9639 for switching to keyboard displayis displayed in the touch panel, keyboard buttons can be displayed onthe display portion 9631 b.

Touch input can be performed concurrently on the touch panel areas 9632a and 9632 b.

The display-mode switching button 9034 allows switching between alandscape mode and a portrait mode, color display and black-and-whitedisplay, and the like. With the power-saving-mode switching button 9036,the luminance of display can be optimized in accordance with the amountof external light at the time when the tablet terminal is in use, whichis detected with an optical sensor incorporated in the tablet terminal.The tablet terminal may include another detection device such as asensor for detecting orientation (e.g., a gyroscope or an accelerationsensor) in addition to the optical sensor.

Although the display portion 9631 a and the display portion 9631 b havethe same display area in FIG. 12A, one embodiment of the presentinvention is not limited to this example. The display portion 9631 a andthe display portion 9631 b may have different areas or different displayquality. For example, one of them may be a display panel that candisplay higher-definition images than the other.

The tablet terminal is closed in FIG. 12B. The tablet terminal includesthe housing 9630, a solar battery 9633, a charge/discharge controlcircuit 9634, a battery 9635, and a DCDC converter 9636. Note that inFIG. 12B, a structure including a battery 9635 and a DCDC converter 9636is illustrated as an example of the charge/discharge control circuit9634.

Since the tablet terminal can be folded in two, the housing 9630 can beclosed when the tablet is not in use. Thus, the display portions 9631 aand 9631 b can be protected, thereby providing a tablet terminal withhigh endurance and high reliability for long-term use.

The tablet terminal illustrated in FIGS. 12A and 12B can have otherfunctions such as a function of displaying various kinds of data (e.g.,a still image, a moving image, and a text image), a function ofdisplaying a calendar, a date, the time, or the like on the displayportion, a touch-input function of operating or editing the datadisplayed on the display portion by touch input, and a function ofcontrolling processing by various kinds of software (programs).

The solar battery 9633, which is attached on a surface of the tabletterminal, can supply electric power to a touch panel, a display portion,an image signal processor, and the like. Note that the solar battery9633 can be provided on one or both surfaces of the housing 9630 and thebattery 9635 can be charged efficiently. When a lithium ion battery isused as the battery 9635, there is an advantage of downsizing or thelike.

The structure and operation of the charge/discharge control circuit 9634illustrated in FIG. 12B are described with reference to a block diagramof FIG. 12C. FIG. 12C illustrates the solar battery 9633, the battery9635, the DCDC converter 9636, a converter 9637, switches SW1 to SW3,and the display portion 9631. The battery 9635, the DCDC converter 9636,the converter 9637, and the switches SW1 to SW3 correspond to thecharge/discharge control circuit 9634 in FIG. 12B.

First, an example of operation in the case where power is generated bythe solar battery 9633 using external light is described. The voltage ofpower generated by the solar battery 9633 is raised or lowered by theDCDC converter 9636 so that a voltage for charging the battery 9635 isobtained. When the display portion 9631 is operated with the power fromthe solar battery 9633, the switch SW1 is turned on and the voltage ofthe power is raised or lowered by the converter 9637 to a voltage neededfor operating the display portion 9631. In addition, when display on thedisplay portion 9631 is not performed, the switch SW1 is turned off anda switch SW2 is turned on so that charge of the battery 9635 may beperformed.

Here, the solar battery 9633 is shown as an example of a powergeneration means; however, there is no particular limitation on a way ofcharging the battery 9635, and the battery 9635 may be charged withanother power generation means such as a piezoelectric element or athermoelectric conversion element (Peltier element). For example, thebattery 9635 may be charged with a non-contact power transmission modulethat transmits and receives power wirelessly (without contact) to chargethe battery or with a combination of other charging means.

In a television device 8000 in FIG. 13A, a display portion 8002 isincorporated in a housing 8001. The display portion 8002 displays animage and a speaker portion 8003 can output sound.

The display device described in Embodiment 5 can be used for the displayportion 8002, and in the case of using the display device, thereliability of the display portion 8002 can be improved.

The television device 8000 may be provided with a receiver, a modem, andthe like. With the receiver, the television device 8000 can receivegeneral television broadcasting. Furthermore, when the television device8000 is connected to a communication network by wired or wirelessconnection via the modem, one-way (from a transmitter to a receiver) ortwo-way (between a transmitter and a receiver, between receivers, or thelike) data communication can be performed.

In addition, the television device 8000 may include a CPU for performinginformation communication or a memory. The CPU described in Embodiment 4can be used in the television device 8000.

In FIG. 13A, an air conditioner including an indoor unit 8200 and anoutdoor unit 8204 is an example of an electronic appliance including theCPU of Embodiment 6. Specifically, the indoor unit 8200 includes ahousing 8201, an air outlet 8202, a CPU 8203, and the like. FIG. 13Ashows the case where the CPU 8203 is provided in the indoor unit 8200;the CPU 8203 may be provided in the outdoor unit 8204. Alternatively,the CPU 8203 may be provided in both the indoor unit 8200 and theoutdoor unit 8204. By using the CPU described in Embodiment 4 as the CPUin the air conditioner, power consumption can be reduced.

In FIG. 13A, an electric refrigerator-freezer 8300 is an example of anelectronic appliance which is provided with the CPU formed using anoxide semiconductor. Specifically, the electric refrigerator-freezer8300 includes a housing 8301, a door for a refrigerator 8302, a door fora freezer 8303, a CPU 8304, and the like. In FIG. 13A, the CPU 8304 isprovided in the housing 8301. When the CPU described in Embodiment 4 isused as the CPU 8304 of the electric refrigerator-freezer 8300, powersaving can be achieved.

FIG. 13B illustrates an example of an electric vehicle which is anexample of an electronic appliance. An electric vehicle 9700 is equippedwith a secondary battery 9701. The output of the electric power of thesecondary battery 9701 is adjusted by a control circuit 9702 and theelectric power is supplied to a driving device 9703. The control circuit9702 is controlled by a processing unit 9704 including a ROM, a RAM, aCPU, or the like which is not illustrated. When the CPU described inEmbodiment 4 is used as the CPU in the electric vehicle 9700, powersaving can be achieved.

The driving device 9703 includes a DC motor or an AC motor either aloneor in combination with an internal-combustion engine. The processingunit 9704 outputs a control signal to the control circuit 9702 based oninput data such as data of operation (e.g., acceleration, deceleration,or stop) by a driver or data during driving (e.g., data on an upgrade ora downgrade, or data on a load on a driving wheel) of the electricvehicle 9700. The control circuit 9702 adjusts the electric energysupplied from the secondary battery 9701 in accordance with the controlsignal of the processing unit 9704 to control the output of the drivingdevice 9703. In the case where the AC motor is mounted, although notillustrated, an inverter which converts direct current into alternatecurrent is also incorporated.

This embodiment can be implemented combining with another embodiment asappropriate.

This application is based on Japanese Patent Application serial no.2012-178723 filed with Japan Patent Office on Aug. 10, 2012, the entirecontents of which are hereby incorporated by reference.

What is claimed is:
 1. A semiconductor device comprising: a first oxidesemiconductor film; a second oxide semiconductor film having acrystalline structure over the first oxide semiconductor film; and athird oxide semiconductor film over the second oxide semiconductor film,wherein a bottom of a conduction band in the second oxide semiconductorfilm is deeper from a vacuum level than a bottom of a conduction band inthe first oxide semiconductor film and a bottom of a conduction band inthe third oxide semiconductor film.
 2. The semiconductor deviceaccording to claim 1, wherein a concentration of Si contained in each ofthe first oxide semiconductor film and the third oxide semiconductorfilm is lower than or equal to 3×10¹⁸/cm³.
 3. The semiconductor deviceaccording to claim 1, wherein a concentration of carbon contained ineach of the first oxide semiconductor film and the third oxidesemiconductor film is lower than or equal to 3×10¹⁸/cm³.
 4. Thesemiconductor device according to claim 1, wherein the second oxidesemiconductor film includes a crystal region which is c-axis-aligned ina direction substantially perpendicular to a surface of the second oxidesemiconductor film.
 5. The semiconductor device according to claim 1,wherein the first oxide semiconductor film and the third oxidesemiconductor film each have an indium content of higher than or equalto 1×10¹⁹/cm³.
 6. The semiconductor device according to claim 1, whereinthe second oxide semiconductor film has a higher indium content than thefirst oxide semiconductor film and the third oxide semiconductor film.7. The semiconductor device according to claim 1, wherein the firstoxide semiconductor film and the third oxide semiconductor film containindium, zinc, and gallium.
 8. The semiconductor device according toclaim 1, wherein the second oxide semiconductor film has an absorptioncoefficient due to a localized state of less than or equal to 3×10⁻³/cm.9. The semiconductor device according to claim 1, wherein the thirdoxide semiconductor film has a lower degree of crystallinity than thesecond oxide semiconductor film.
 10. The semiconductor device accordingto claim 1, wherein the first oxide semiconductor film has a lowerdegree of crystallinity than the second oxide semiconductor film.
 11. Asemiconductor device comprising: a first nitride insulating film; afirst oxide semiconductor film over the first nitride insulating film; asecond oxide semiconductor film having a crystalline structure over thefirst oxide semiconductor film; a third oxide semiconductor film overthe second oxide semiconductor film; and a second nitride insulatingfilm over the third oxide semiconductor film, wherein a bottom of aconduction band in the second oxide semiconductor film is deeper from avacuum level than a bottom of a conduction band in the first oxidesemiconductor film and a bottom of a conduction band in the third oxidesemiconductor film.
 12. The semiconductor device according to claim 11,wherein a concentration of Si contained in each of the first oxidesemiconductor film and the third oxide semiconductor film is lower thanor equal to 3×10¹⁸/cm³.
 13. The semiconductor device according to claim11, wherein a concentration of carbon contained in each of the firstoxide semiconductor film and the third oxide semiconductor film is lowerthan or equal to 3×10¹⁸/cm³.
 14. The semiconductor device according toclaim 11, wherein the second oxide semiconductor film includes a crystalregion which is c-axis-aligned in a direction substantiallyperpendicular to a surface of the second oxide semiconductor film. 15.The semiconductor device according to claim 11, wherein the first oxidesemiconductor film and the third oxide semiconductor film each have anindium content of higher than or equal to 1×10¹⁹/cm³.
 16. Thesemiconductor device according to claim 11, wherein the second oxidesemiconductor film has a higher indium content than the first oxidesemiconductor film and the third oxide semiconductor film.
 17. Thesemiconductor device according to claim 11, wherein the first oxidesemiconductor film and the third oxide semiconductor film containindium, zinc, and gallium.
 18. The semiconductor device according toclaim 11, wherein the second oxide semiconductor film has an absorptioncoefficient due to a localized state of less than or equal to 3×10⁻³/cm.19. The semiconductor device according to claim 11, wherein the thirdoxide semiconductor film has a lower degree of crystallinity than thesecond oxide semiconductor film.
 20. The semiconductor device accordingto claim 11, wherein the first oxide semiconductor film has a lowerdegree of crystallinity than the second oxide semiconductor film.